Structure for wiring reliability evaluation test and semiconductor device having the same

ABSTRACT

A test line (12) is formed between a pair of current sypplying terminals (11). A step pattern (14) composed of polysilicon or the like is formed below the test line (12) through an inter-layer insulation film. One of two sides of the step pattern (14) that extends along the longitudinal direction of the test line (12) is positioned therebelow so as to form a step extending in a direction of the test line. Thus, since electromigration tends to easily take place, the deterioration of the semiconductor device can be precisely evaluated.

This application is a continuation of U.S. patent application Ser. No.08/326,269, filed Oct. 20, 1994 now abandoned.

FIELD OF THE INVENTION

The present invention relates to a semiconductor device and, inparticular, to a semiconductor device having a structure for wiringreliability evaluation test.

BACKGROUND OF THE INVENTION

As the size of wiring lines in the semiconductor device decreases, thedensity of currents that flow therein increases. Thus, electromigrationtakes place and is becoming a problem of the reliability of wiringlines. To evaluate withstanding characteristics of the wiring linesagainst the electromigration, the following test is conventionallyperformed. As shown in FIG. 1, a wiring pattern with a test line 12 andboth a pair of current supplying terminals 11 and a pair of voltagemeasuring terminals 13 is formed on an insulation film. A cover film(passivation film) having holes for the terminals (pad portions) isformed. Thereafter, pelletizing, bonding, and packaging processes areperformed. The resultant semiconductor device is placed in a thermostat.A constant current is supplied to the current supplying terminals 11 andthe voltage of the test line is measured at voltage measuring terminals13. The temperature of the thermostat and the density of currentsupplied via the current supplying terminals 11 are varied in apredetermined number of levels. For each level, a predetermined numberof samples, for example 10 samples, are tested. The time period aftereach sample is tested until a line breakage takes place, or the lineresistance exceeds a predetermined value, is referred to as failuretime. Assuming logarithmic normal distribution or Weibull distribution,mean failure time of all the samples is obtained.

Thus, since current acceleration coefficient and activation energy areobtained on the basis of the above result, the life time of the wiringof a semiconductor device at a temperature and a current density atwhich the semiconductor device is operated can be estimated.

However, it is known that the life time of the wiring is also influencednot only by the structure and film quality of the wiring lines but alsoby the flatness of an inter-layer insulation film on which the wiring isformed. To solve such a problem, a method where step patterns 14 areformed below a test line 12, as shown in FIG. 2, is known and describedin "Step Spacing Effect on Electromigration", Proc. 1990, IEEE/IRPS, pp.20-24, 1990.

In the semiconductor device that was designed corresponding to theabove-mentioned test, no problem should take place on theelectromigration. However, due to a failure in the fabrication stage orthe like, the life time of the semiconductor device may be shorter thanexpected. To detect a failure in the fabrication stage, a structure forwiring reliability evaluation test is formed on a product or on the samewafer thereof. On the wafer, an ultra-high acceleration test isperformed so as to verify the wiring. As an evaluation pattern that hasbeen widely used for such a purpose a pattern shown in FIG. 3 is knownother than the above-mentioned pattern. Referring to FIG. 3, protrusionportions 22a are formed in a test line 22. The test line 22 is connectedbetween current supplying terminals 21. From the current supplyingterminals 21, a current is supplied. The temperature of narrow lineportions formed between the protrusion portions 22a is raised by thecurrent. Thus, the test can be performed without need to use an externalheat source. When the semiconductor device is tested corresponding tothe abovementioned method, if the failure time is shorter than thepredetermined value, it is determined that a failure took place in thefabrication process. Thus, the wafer including the failure semiconductordevice, or the lot thereof, is treated as a failure wafer, or a failurelot, and prevented from being placed on the market.

With the wiring patterns shown in FIGS. 1 and 3, since the patterns areformed on a flat surface, the patterns do not well simulate the wiringof the real semiconductor devices, which have step patterns formed belowthe wiring. Thus, with such patterns, the failures of the productscannot be satisfactorily detected. As stated in the above-mentioneddocument, as long as the step coverage (film thickness of stepportion/film thickness of flat portion) is not very low (for example10%), the failure time of the wiring pattern with the step patternsformed therebelow, as shown in FIG. 2, is not remarkably affected.

Thus, in the conventional wiring reliability evaluation test structure,deterioration and failure time cannot be accurately estimated.Consequently, failure products cannot be prevented from being placed onthe market.

SUMMARY OF THE INVENTION

An object of the present invention is to propose a structure for wiringreliability evaluation test that can well simulate a real wiring and topropose a test wiring that tends to more easily cause electromigrationthan the wiring of a real product, so as to precisely estimate thefailure time of the product and to prevent failure products from beingplaced on the market.

A first aspect of the present invention is a wiring reliabilityevaluation test structure, comprising a substrate, at least one steppattern formed above the substrate, an interlayer insulation film formedabove the substrate in such a manner that the inter-layer insulationfilm covers the step pattern, and a test line formed above theinter-layer insulation film in such a manner that the test line passesthrough a region corresponding to the step pattern, wherein the steppattern has an outer peripheral portion that extends in the regioncorresponding to the test line in a direction that is not perpendicularto a current direction of the test line.

A second aspect of the present invention is a semiconductor substrate onwhich a functional circuit portion is formed and a wiring reliabilityevaluation test structure, the structure including at least one steppattern formed above the semiconductor substrate, an inter-layerinsulation film formed above the semiconductor substrate in such amanner that the interlayer insulation film covers the step pattern, anda test line formed above the inter-layer insulation film in such amanner that the test line passes through a region corresponding to thestep pattern, wherein the step pattern has an outer peripheral portionthat extends in the region corresponding to the test line in a directionthat is not perpendicular to a current direction of the test line.

In one embodiment of the present invention, at least one step pattern isfully covered by the test line through the inter-layer insulation film.

In one embodiment of the present invention, at least one step pattern ispartially covered by the test line through the inter-layer insulationfilm.

In one embodiment of the present invention, a plane of the step patternis formed in a parallelogram shape.

In one embodiment of the present invention, a section of the steppattern is formed in a parallelogram shape or a shape having aprotrusion portion that protrudes upwardly from the parallelogram.

In one embodiment of the present invention, the step pattern is composedof at least one material taken from a group including polysilicon,polycide, silicide, a metal or an insulator, or is a laminate comprisinga plurality of films each composed of at least one material taken from agroup including polysilicon, polycide, silicide, a metal or aninsulator.

In one embodiment of the present invention, the test line is composed ofeither aluminum or an alloy thereof, or is a laminate of a first filmcomposed of either aluminum or an alloy thereof and a second filmcomposed of either a high melting point metal or alloy such as W, TiNand TiW.

In one embodiment of the present invention, the test line has apredetermined width and is formed in a straight shape or a zigzag shape.

In one embodiment of the present invention, the test line has a narrowportion and a wide portion, the step pattern being formed at a regioncorresponding to the narrow portion.

In one embodiment of the present invention, current supplying terminalsformed at the ends of the test line are used.

In one embodiment of the present invention, the current supplyingterminals are connected to external leads through respective bondingwires.

In one embodiment of the present invention, voltage measuring terminalsformed at the ends of the test line are used.

In one embodiment of the present invention, there is used a passivationfilm formed above the inter-layer insulation film in such a manner thatthe passivation film covers the test line except for the currentsupplying terminals.

In one embodiment of the present invention, the semiconductor substrateand the wiring reliability evaluation test structure being covered witha mold resin.

According to the wiring reliability evaluation test structure of thepresent invention, step patterns are formed below a test line so thatthe step is formed along the longitudinal direction of the test line,grain boundaries that largely influence the electromigration tend to beformed along the longitudinal direction of the test line. Thus,according to the present invention, the deterioration of the product dueto failures of the inter-layer insulation films, the wiring and thepassivation film can be more precisely or more strictly evaluated.Consequently, the failure products can be prevented from being placed onthe market. In addition, according to the present invention, since thewiring reliability evaluation test structure can be formed in theconventional fabrication process of the product without need to useextra processes, the fabrication cost is not raised.

These and other objects, features and advantages of the presentinvention will become more apparent in light of the following detaileddescription of best mode embodiments thereof, as illustrated in theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing a conventional test wiring;

FIG. 2 is a plan view showing a conventional wiring reliabilityevaluation test structure;

FIG. 3 is a plan view showing a conventional test wiring;

FIG. 4 is a partially cut away, plan view showing a semiconductor devicehaving a wiring reliability evaluation test structure according to thepresent invention;

FIG. 5A is a plan view showing a test structure portion of thesemiconductor device of FIG. 4;

FIG. 5B is a partially enlarged view of FIG. 5A;

FIG. 6A is a sectional view taken along line A-A' of FIG. 5B;

FIG. 6B is another sectional view taken along line A-A' of FIG. 5B;

FIG. 7A is a plan view showing a generation of grain boundaries of thesemiconductor device according to the present invention;

FIG. 7B is a plan view showing another generation of grain boundaries ofthe semiconductor device according to the present invention;

FIG. 8A is a plan view showing a modification of the semiconductordevice according to the present invention;

FIG. 8B is a plan view showing another modification of the semiconductordevice according to the present invention;

FIG. 8C is a plan view showing a further modification of thesemiconductor device according to the present invention;

FIG. 9 is a plan view showing another test structure portion of thesemiconductor device according to the present invention; and

FIG. 10 is a sectional view showing a test structure according to thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Next, with reference to the accompanying drawings, embodiments of thepresent invention will be described.

FIG. 4 is a partially cut away view showing a semiconductor devicehaving a wiring reliability evaluation test structure according to afirst embodiment of the present invention. Referring to FIG. 4,reference numeral 10 denotes a semiconductor substrate composed ofsilicon or the like. Reference numeral 2 denotes an external lead.Reference numeral 3 denotes a mold resin. On the substrate 10, afunctional circuit portion 4 essential to the semiconductor device and awiring reliability evaluation test structure portion 5 are formed.Reference numeral 6 denotes an electrode pad for electrically connectingboth the functional circuit portion 4 and the test structure portion 5to the outside of the semiconductor device. Reference numeral 7 denotesa bonding wire that electrically connects the electrode pad 6 with theexternal lead 2.

FIG. 5A is a plan view showing the test structure portion 5 of thesemiconductor device according to the present invention. FIG. 5B is apartially enlarged view of FIG. 5A. Referring to FIG. 5A, a test line 12is formed between a pair of current supplying terminals 11. Voltagemeasuring terminals 13 are formed adjacent to the respective currentsupplying terminals 11. The current supplying terminals 11 and thevoltage measuring terminals 13 are equivalent to the electrode pads 6shown in FIG. 4. The length and width of the line 12 are 500 μm and 2μm, respectively. In addition, the line 12 is formed straight. The teststructure portion 5 is formed along with the functional circuit portion4 in the fabrication process of the semiconductor device. Thus, the filmquality of the wiring, the flatness of the inter-layer insulation film,the film quality of the passivation film, and so forth of the teststructure portion 5 are the same as those of the functional circuitportion 4.

Referring to FIG. 5B, step patterns 14 are formed below the test line 12through an inter-layer insulation film. The step patterns 14 arecomposed of polysilicon (see FIGS. 6A and 6B). In FIG. 5B, only two steppatterns are shown. However, in reality, many step patterns are formed.The plane of the step patterns 14 is a parallelogram shape, preferably,a rectangle shape with outer peripheral portions 30. One of parallelsides of the step pattern 14 that are in parallel with the line 12 ispositioned therebelow. Thus, a step that extends in the longitudinaldirection of the line 12 is formed below the line 12.

FIGS. 6A and 6B are sectional views taken along line A-A' of FIG. 5B.FIGS. 7A and 7B are plan views showing generation states of grainboundaries of the test line 12 together with the step patterns 14 havingouter peripheral portions 30. In FIGS. 6A and 7A, an inter-layerinsulation film that has been normally formed is shown. In FIGS. 6B and7B, an inter-layer insulation film that has been abnormally formed isshown.

Referring to FIGS. 6A and 6B, the step patterns 14 composed ofpolysilicon are formed on the semiconductor substrate 10. Theinter-layer insulation film 15 is formed above the semiconductorsubstrate 10 so as to cover the step patterns 14. The test line 12 thatis composed of an aluminum alloy is formed above the insulation film 15.In addition, a passivation film 16 is formed above the insulation film15 so as to cover the test line 12. However, the passivation film 16 isnot formed on the terminal portions (electrode pads).

As shown in FIGS. 6A and 7A, when the inter-layer insulation film 15 issmoothly (normally) formed, grain boundaries 17 are formed perpendicularto the longitudinal direction of the test line 12. In contrast, as shownin Figs. GB and 7B, when the inter-layer insulation film 15 is notsmoothly formed, the grain boundaries 17 tends to be formed in thedirection of the test line parallel with the step. When the grainboundaries 17 are formed along the longitudinal direction of the testline 12, aluminum atoms tend to travel due to occurrence ofelectromigration, thereby decreasing the failure time.

Since the wiring reliability evaluation test means shown in the drawingsis formed in the fabrication process of the real product, if films ofthe real product are abnormally formed, the inter-layer insulation filmand the test line of the wiring reliability evaluation test means areinfluenced. Thus, after the wafer process is completed or the productfabrication is completed, the resultant sample is positioned on aheating stage of 200° C., then a current is supplied to the currentsupplying terminals 11 in such a manner that the current density becomes1×10⁷ A/cm². At this point, by measuring the electromigration failuretime, the life time of the product can be precisely expected.

On the other hand, the reason why the failure time of a real wiringcannot be simulated with the test line 12 shown in FIG. 2 would be asfollows. Since the test line 12 intersects with the step patterns 14that are formed perpendicular to the longitudinal direction of the line12, the grain boundaries of the test line (Al) 12 are formedperpendicular to the longitudinal direction thereof. Theelectromigration of the test line 12 takes place due to the traveling ofaluminum atoms in the current direction, the aluminum atoms tend totravel along the grain boundaries of the test line 12. Thus, in theconventional test wiring, where the grain boundaries are not formed inthe current direction, the progress of the electromigration issuppressed. However, in a real wiring, step patterns 14 may extend inthe longitudinal direction of a wiring line. In this case, the grainboundaries of the line tend to be formed in the longitudinal directionthereof (namely, the current direction). Thus, the progress of theelectromigration of the wiring of the functional circuit portion may befaster than that of the test wiring.

FIGS. 8A, 8B and 8C are schematic diagrams showing modifications of thefirst embodiment of the present invention. FIGS. 8A, 8B and 8Ccorrespond to FIG. 5B. Referring to FIG. 8A, a test line 12 is formedabove a sequence of step patterns 14 having outer peripheral portion 30,so that the test line 12 passes through one side of each step pattern14, the side being parallel to the test line 12. Referring to FIG. 8B, atest line 12 is formed so that it fully covers a step pattern 14.Referring to FIG. 8C, a test line 12 is formed above a sequence of steppatterns 14 that are formed in a zigzag shape so that the test line 12passes through the center line of the zigzag shape of sequence. In eachof the modifications, the step patterns 14 have an outer peripheralportion that extends along the test line 12.

The selection of these step patterns, the length and width of the testline, and the number of step patterns formed below the test line dependson the wiring construction of the real product to be evaluated.

FIG. 9 is a plan view showing a test structure portion of asemiconductor device according to a second embodiment of the presentinvention. In the second embodiment, a pattern similar to that shown inFIG. 3 is used. Referring to FIG. 9, a test line 22 is formed between apair of current supplying terminals 21. The test line 22 has a pluralityof protrusion portions 22a that are cyclically formed. In addition, aswith the first embodiment, step patterns 24 are formed below a narrowline portion that is positioned between the protrusion portions 22a. Thestructure of the other portions of the second embodiment is the same asthat of the first embodiment.

In the second embodiment, a wiring reliability evaluation test isperformed by measuring the failure time, which is a time period after acurrent is supplied until the test line is broken.

FIG. 10 is a sectional view showing another test structure portion of asemiconductor device according to the present invention. Referring toFIG. 10, a first polysilicon film 14a, a first inter-layer insulationfilm 15a, a second polysilicon film 14b and a second inter-layerinsulation film 15b are formed above a substrate 10. Reference numeral12 denotes a test line. Reference numeral 16 denotes a passivation film.In this embodiment, the first polysilicon film 14a, the firstinter-layer insulation film 15a and the second polysilicon film 14bconstructs a step pattern. The step pattern has a protrusion portionthat protrudes upwardly from a rectangle portion.

According to the above-described embodiments, since the semiconductordevice has a wiring reliability evaluation test structure, even if allthe processes including the packaging process are completed, the finalproduct can be evaluated. In addition, after the wafer process iscompleted, the wafer can be evaluated so as to detect a failure product.

According to the present invention, both the above-mentioned wiringreliability evaluation test structure formed in a semiconductor deviceand a wiring reliability evaluation test structure that is not formed ina semiconductor device are provided. The former was shown in theabove-described embodiments. The latter is, for example, a structurethat is formed at a first portion of the wafer where the semiconductordevice having a functional circuit portion is formed at the secondportion other than the first portion. Thus, after the wafer process iscompleted, the life time of the semiconductor device that ismanufactured by using the same wafer can be precisely predicted.

The preferred embodiments of the present invention were described.However, the present invention is not limited to such embodiments. Inthe above-described embodiments, the polysilicon film was used to formthe step patterns. However, polycide or silicide may be used instead ofpolysilicon. In addition, with a first-layered metal line of amulti-layer wiring that is used as step patterns, a second-layered linemay be tested. Moreover, as described above, step patterns that arecomposed of a composite film of such films may be used. The test line(wiring pattern) may be formed in a zigzag shape instead of straightshape. The test line may be composed of aluminum or an alloy thereof, ormay be a laminate of a first film composed of aluminum or an alloythereof and a second film composed of a high melting point metal oralloy such as W, TiN and TiW.

Although the present invention has been shown and described with respectto best mode embodiments thereof, it should be understood by thoseskilled in the art that the foregoing and various other changes,omissions and additions in the form and detail thereof may be madetherein without departing from the spirit and scope of the presentinvention.

What is claimed is:
 1. A semiconductor device comprising a semiconductorsubstrate having a major surface on which a functional circuit portionis formed and a wiring reliability evaluation test structure, saidstructure including:at least one step pattern formed on said majorsurface of said semiconductor substrate; an inter-layer insulation filmformed on said major surface of said semicondutor substrate in suchmanner that said inter-layer insulation film covers said step pattern;and a test line formed on said inter-layer insulation film in such amanner that said test line passes through a region corresponding to saidstep pattern as viewed in a direction perpendicular to said majorsurface. said step pattern being an outer peripheral portion thatextends, as viewed in a direction perpendicular to said major surface,in the region corresponding to said test line, said outer peripheralportion extending in a direction that is not perpendicular to a currentdirection of said test line, in a region corresponding to said testline, current supplying terminals formed at ends of said test line, saidcurrent supplying terminals being connected to external leads throughrespective bonding wires.
 2. The structure as set north in claim 1,wherein said at least one step pattern is fully covered by said testline.
 3. The structure as set forth in claim 1, wherein the at least onestep pattern is partially covered by said test line.
 4. The structure asset forth in claim 1, wherein a plane of said at least one step patternis formed in a parallelogram shape.
 5. The structure as set forth inclaim 1, wherein a section of said at least one step pattern is formedin a parallelogram shape having a protrusion portion that protrudes fromthe parallelogram in a upward direction relative to said major surfaceof said substrate.
 6. The structure as set forth in claim 1, whereinsaid step pattern is composed of a material taken from a groupconsisting of polysilicon, polycide, silicide, a metal, an insulator, alaminate comprising a plurality of films each composed of a materialtaken from a group consisting of polysilicon, polycide, silicide, ametal, and an insulator.
 7. The structure as set forth in claim 1,wherein said test line is composed of a material taken from a groupconsisting of aluminum, an alloy thereof, and a laminate of a first filmcomposed of a material taken from a group consisting of aluminum and analloy thereof and a second film composed of a material taken from agroup consisting of a high melting point metal and alloy such as W, TiNand TiW.
 8. The structure as set forth in claim 1, wherein said testline has a predetermined width and is formed in a pattern taken from agroup consisting of a straight shape and a zigzag shape.
 9. Thestructure as set forth in claim 1, wherein said test line has a narrowportion and a wide portion, said at least one step pattern being formedat a region corresponding to the narrow portion.
 10. The structure asset forth in claim 1, further comprising current supplying terminalsformed at ends of said test line.
 11. The structure as set forth inclaim 10, further comprising voltage measuring terminals formed at endsof said test line.
 12. A semiconductor device comprising a semiconductorsubstrate having a major surface on which a functional circuit portionis formed and a wiring reliability evaluation test structure, saidstructure including:at least one step pattern formed on said majorsurface of said semiconductor substrate; an inter-layer insulation filmformed on said major surface of said semiconductor substrate in such amanner that said inter-layer insulation film covers said step pattern;and a test line formed on said inter-layer insulation film in such amanner that said test line passes through a region corresponding to saidstep pattern, current supplying terminals formed at ends of said testline, said test line being electrically isolated from said step patternby said inter-layer insulation film, a passivation film formed on saidinter-layer insulation film in such a manner that said passivation filmcovers said test line except for said current supplying terminals, saidstep pattern having an outer peripheral portion that extends into aregion corresponding to said test line, said outer peripheral portionextending in a direction that is not perpendicular to a direction ofcurrent in said test line, in the region where said test line passessaid step pattern, and said test line and at least a portion of saidstep pattern being overlapped via said inter-layer insulation film sothat said outer peripheral portion of said step pattern extends undersaid test line in a direction parallel to a direction of said test line.13. A semiconductor device comprising a semiconductor substrate having amajor surface on which a functional circuit portion is formed and awiring reliability evaluation test structure, said structureincluding:at least one step pattern formed on said major surface of saidsemiconductor substrate; an inter-layer insulation film formed on saidmajor surface of said semiconductor substrate in such a manner that saidinter-layer insulation film covers said step pattern; and a test lineformed on said inter-layer insulation film in such a manner that saidtest line passes through a region corresponding to said step pattern,current supplying terminals formed at ends of said test line, said testline being electrically isolated from said step pattern by saidinter-layer insulation film, a passivation film formed on saidinter-layer insulation film in such a manner that said passivation filmcovers said test line except for said current supplying terminals, saidsemiconductor substrate and the wiring reliability evaluation teststructure being covered with a molded resin material, said step patternhaving an outer peripheral portion that extends into a regioncorresponding to said test line, said outer peripheral portion extendingin a direction that is not perpendicular to a direction of current insaid test line, in the region where said test line passes said steppattern, and said test line and at least a portion of said step patternbeing overlapped via said inter-layer insulation film so that said outerperipheral portion of said step pattern extends under said test line ina direction parallel to a direction of said test line.